The present invention is related to a highly integrated erasable programmable read only memory (EPROM) device and a process to fabricate it. More precisely, it is related to an EPROM whose device packing density is increased by utilizing a self alignment technique.
It is important to cut down a marginal space in circuit pattern in order to increase the packing density of element devices on the IC. The self alignment technique is one of effective methods to cut down the marginal space for photolithographic mask alignment process for fabricating the ICs.
In ordinary EPROM devices which is composed of MOS-FET (metal-oxide-semiconductor type field effect transistor) having a floating gate, the self alignment is applied to cut down the marginal space on both sides of gate to determine the length of a gate of the FETs. But it is necessary to leave a margin for mask alignment to determine the width of the floating gate. Such situation will be explained briefly with respect to FIGS. 1 and 2.
FIG. 1 is a plan view of an elementary memory cell of an EPROM device, schematically illustrating steps of its fabrication process, while FIG. 2 is a sectional view along the line AA and seen in the direction of arrows in FIG. 1 corresponding to respective fabrication steps. As shown in FIGS. 1(a) and 2(a), on a p-type silicon substrate 1 for example, is fabricated a silicon dioxide (SiO.sub.2) film 2 by ordinary selective oxidation. This SiO.sub.2 film is patterned like islands arranged in a matrix on the substrate 1 for separating the devices between each other. Such SiO.sub.2 layers are called as field oxide layer.
Next, as shown in FIGS. 1(b) and 2(b), the entire surface of the substrate is covered with a first gate oxide film 3 of SiO.sub.2 which is formed by thermal oxidation. Subsequently, the surface is covered by a first conductive polysilicon layer (PA) 5. The first polysilicon layer 5 is patterned to form stripes separated from each other by grooves 4 which are formed by etching. Each of the groove 4 is positioned on the center of a column of the field oxide layer 2, so, the field oxide layer 2 is exposed at its center part. Each stripes having a width W.sub.F bridges between the adjacent columns of the field oxide layers 2 as shown in FIG. 1(b). The width W.sub.F of the stripe becomes later the width of the floating gate of the FET. The direction of the line AA in FIG. 1 or the direction of the width W.sub.F in FIG. 2 will be referred to as a direction of gate width, and the direction orthogonal to it, namely the direction of the arrows in FIG. 1 will be referred to as a direction of gate length hereinafter.
Subsequently, as shown in FIGS. 1(c) and 2(c), the entire surface of the substrate is covered with second gate oxide film 6 by thermal oxidation. Next, the surface is covered by second conductive polysilicon layer (PB) 7. Then, the second gate oxide layer 6 and the stripes of the first polysilicon layer 5 are selectively etched off leaving a second stripes which are orthogonal to the grooves 4. The second stripes have a predetermined width W.sub.C which becomes later the gate length of the FET. By this etching process, the protions of the first stripes 5 which are covered by the second stripes 7 become the gate 8 of the FETs. And the second stripes 7 become control gate. They are extended in horizontal direction in the figure, and become word lines. Like such a manner, the floating gates 8 are formed underneath the control gate 7 separated from it by the second gate oxide film 6. The width and length of the floating gates 8 are respectively W.sub.F and W.sub.C.
Then, the surface of the p-type silicon substrate 1 exposed from the second stripe are doped by n-type impurities by ion implantation, for example, to from n.sup.+ -type source 9 and drain 10.
Though in FIG. 1(c) the floating gate 8 is shown by a broken line slightly narrower than the control gate 7 in order to identify it, but as can be understood from the above explanation, the control gate 7 and the floating gate 8 are self aligned to each other and have a substantially same width, because the floating gate 8 is etched using the self alignment technique utilizing the control gate 7 as a mask. Therefore, there is no need to prepare a marginal space for mask alignment between the control gate and the floating gate in the direction of the gate length. So, the packing density of the FETs in the direction of their gate length is increased to the limit determined by resolution of photolithography. But in the direction orthogonal to it (in the direction of gate width), on the contrary, the marginal space is necessary.
As has been described before, the grooves 4 in FIGS. 1 and 2 must be aligned to respective column of the field oxide layers 2. Since the grooves 4 are formed by photolithographic etching, it is necessary, as shown in FIGS. 1(c) and 2(c), to provide a marginal space W.sub.A on both sides of the grooves 4 having a width W.sub.S. In the present-state-of-the-art photolithography, the marginal spaces W.sub.A of approximately 0.3-0.5 .mu.m are necessary on both sides of a groove having width W.sub.S of 0.6-1 .mu.m for example. Therefore, the packing density of the FETs in the direction of gate width can not be increased to the limit determined by the resolution of photolithography.
Another fact to decrease the packing density in the direction of gate width are invalid spaces under the both sides of the floating gate width W.sub.F in FIG. 2(b). These invalid spaces are identified by 11 in FIG. 2. They are called in the art as "bird's beak". They are inevitably formed on both sides of the field oxide layers 2. The birds beak extends sometimes 1 .mu.m on both side of the field oxide layer 2, and it does contribute neither to the conductance of the FET nor the capacitance of the floating gate. So, desire to cut down these marginal spaces and the bird's beaks is increasing in the large scale integrated EPROMs.
Recently, an attempt to cut down the marginal space for mask alignment by self alignment technique have been proposed by H. Nozawa et al. in "CHARACTERISTICS AND RELIABILITY OF THE SEPROM CELL" in IEEE Trans. ED vol. ED-31, No. 10, October 1984. Schematic diagrams illustrating the fabrication process are shown in FIG. 3. They piled successively on a substrate 21, a first gate oxide layer 23, first conductive polysilicon layer 25 and a silicon nitride film 31. And patterned the silicon nitride film 31 as shown in FIG. 3(a). Then as shown in FIG. 3(b), the first polysilicon layer 25 is oxidized to form the field oxide layers 22 using the silicon nitride film 31 as a mask. After removing the silicon nitride film 31, a second gate oxide layer 26 is formed. Next, second conductive polysilicon layer 27 is formed as shown in FIG. 3(c). Then the substrate is etched like a similar manner of FIGS. 1(c) and 2(c), and is implanted with n-type impurity to form an n.sup.+ -type source 29 and drain 30. A cross sectional view of the device cut along a line from source to drain becomes as shown in FIG. 3(d).
Like a manner described above, the control gate 27 and the floating gate 25 are self aligned to each other. But the bird's beak is still remained. And as can be estimated from the shape of FIG. 3(c), the capacitance between the floating gate and the control gate becomes smaller than that between the floating gate and the channel region. This decreases the sensitivity of the control gate and the programming efficiency of the FET. Moreover, flatness of the surface of the device is not so smooth. This incurs a problem on wiring for interconnecting the devices on the IC chip.